Virtually all complex integrated circuits are designed with the use of computer aided design (CAD) tools. Some CAD tools, called simulators, help the circuit designer verify the operation of a proposed circuit. Another type of CAD tool, called a silicon compiler (also sometimes known as automatic layout or place and route systems), generates the semiconductor mask patterns from a detailed circuit specification. One task that must be performed by a silicon compiler is that it must route connections between the components of the circuit. Such components are often called cells.
The detailed circuit specification used by silicon compilers and circuit simulators is often called a netlist, and comprises a list of circuit components and the interconnections between those components. A short netlist for a simple circuit is shown in Table 1.
TABLE 1 ______________________________________ Exemplary Netlist Cell Input Signals Output Signals Name 1 2 1 2 ______________________________________ XOR A B C XOR C CN1 Y AND A B CA AND C CN1 CB NOR CB CA CN ______________________________________
The netlist defines all of the interconnections between the components of the circuit. Each "signal" which interconnects two or more cells, or which represents an input or output for the entire circuit, is actually a node in the circuit which has been assigned a name. Thus the terms "signal" and "node" are often used interchangeably.
In the exemplary netlist shown in Table 1, signals A, B and CN1 are input nodes to the entire circuit, Y and CN are output nodes for the entire circuit, and nodes C, CA and CB are internal nodes.
In addition, the netlist specifies the nature of its components by specifying a cell name for each component. The cell name, in turn, specifies or points to a particular circuit in a predefined library of cells.
The problem that the present invention solves is as follows. An integrated circuit may have specified timing constraints, which define the maximum allowable amount of time that may take a particular set of input signals to generate output signals on specified output nodes of the circuit. Further, while designing the layout of an integrated circuit there is a tradeoff between the capacitive load on the nodes of the circuit and the difficulty of laying out the circuit. In particular, the capacitance of a node is proportional to the length of that node's connecting lines. Thus, the lower the maximum allowed capacitance on each node of the circuit, the more difficult it is to design or lay out that circuit--because a low node capacitance limits the length of the node's connectors and forces the components coupled to that node to be positioned close to one another.
The capacitive load on each node of the circuit limits the speed with which signal can propagate through that circuit. For instance, if C1 is the capacitance on node CN1 of a circuit, and the component driving node CN1 has a "drive strength" of S, then the timing delay associated with node CN1 is ##EQU1##
The present invention concerns a new type of computer aided design tool--one which helps circuit designers determine the maximum amount of capacitance that should be allowed for each node of a specified circuit. In particular, the present invention provides a system and method for specifying the best possible set of maximum capacitance values for the nodes of circuit. These capacitance values must be consistent with the timing constraints on the circuit, and are selected so as to minimize a "layout difficulty" function which corresponds to the difficulty of designing or laying out a circuit with any given set of capacitive loading constraints.
Referring to FIG. 1, the present invention fills a niche in computer aided design systems which has heretofore remained a task requiring human intervention and engineering expertise. In particular, when designing an integrated circuit using computer aided design (CAD) tools, especially a logic circuit, a netlist 100 representing the particular components is either generated by a logic synthesizer 102 from a logic specification 104 (i.e., a set of boolean equations), or is prepared by an engineer. If the netlist 100 is provided to a silicon compiler 110 or routing program with no limitations on the capacitance of the circuit's nodes, it is quite possible that the resulting circuit layout will not meet the timing requirements for the circuit. As a result, engineers typically specify a set of maximum capacitive loads 114 for at least those nodes on certain critical paths of the circuit. These capacitive loads are then tested using a logic simulator (or logic timing analyzer) 112 so as to ensure that a circuit having nodes with the specified capacitive loads will meet the required timing constraints.
The maximum capacitive loads specified by engineers are often selected based on experience, hunches, and a little bit of calculation based on perceived timing needs at certain critical points of the circuit. In general, it is virtually impossible to accurately compute a set of capacitive constraints by hand. Further, the prior art does not provide a method for selecting the best such set of constraints.